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| DS2435 battery identification chip with time/temperature histogram preliminary DS2435 021798 1/21 features ? provides unique id number to battery packs ? eliminates thermistors by sensing battery tempera- ture onchip ? elapsed time counter provides indication of battery usage/storage time ? time/temperature histogram function provides essential information for determining battery selfdis- charge ? 256bit nonvolatile user memory available for storage of user data such as gas gauge and manufacturing information. ? operating range of 40 c to +85 c ? applications include portable computers, portable/ cellular phones, consumer electronics, and hand held instrumentation. package outline 3 2 1 dallas DS2435 pr35 package gnd dq vdd dallas DS2435 bottom view see mech. drawings section pin description gnd ground dq data in/out v dd supply voltage description the DS2435 battery identification chip provides a con- venient method of tagging and identifying battery packs by manufacturer, chemistry, or other identifying param- eters. the DS2435 allows the battery pack to be coded with a unique identification number, and also store information regarding the battery life and charge/dis- charge characteristics in its nonvolatile memory. the DS2435 also performs the essential function of monitoring battery temperature, without the need for a thermistor in the battery pack. a time/temperature his- togram function stores the amount of time that the bat- tery has been in up to eight temperature bands, allowing more accurate selfdischarge calculations to be carried out by the user for determining remaining battery capac- ity. in addition, the onboard elapsed time counter pro- vides a method of determining the amount of time that a battery pack has been in storage, to allow more accu- rate selfdischarge determination. information is sent to/from the DS2435 over a 1wire tm interface, so that battery packs need only have three output connectors; power, ground, and the 1wire inter- face.
DS2435 021798 2/21 detailed pin description pin symbol description 1 gnd ground pin . 2 dq data input/output pin for 1wire communication port. 3 v dd supply pin input power supply. overview the DS2435 has six major components: 1) scratchpad memory, 2) nonvolatile memory, 3) onboard sram, 4) temperature sensor, 5) id register, and 6) elapsed time counter. all data is read and written least significant bit first. access to the DS2435 is over a 1wire interface. charg- ing parameters and other data such as battery chemis- try, gas gauge information, and other user data would be stored in the DS2435, allowing this information to be permanently stored in the battery pack. nonvolatile (e 2 ) ram holds information even if the battery goes dead; as long as the battery remains within typical charge/dis- charge operating range, the sram provides battery backed storage of information. DS2435 block diagram figure 1 temperature 1wire port measuring circuitry temperature register status register id register cycle counter control logic and memory function control 256bit scratchpad 256bit scratchpad 256bit nonvolatile ram 256bit ram dq elapsed time counter histogram registers DS2435 021798 3/21 DS2435 memory partitioning figure 2 manufacturer id byte 2 histogram bin temp limits temperature (1 c resolution) page 1 user bytes scratchpad ram (sp1) 24 bytes nonvolatile 24 bytes (nv1) page 2 user bytes 8 bytes nonvolatile 8 bytes (nv2) scratchpad ram (sp2) page 3 user bytes 32 bytes 32 bytes sram scratchpad ram (sp3) page 4 sram registers temperature ( 1 / 2 c resolution) status register byte 1 status register byte 2 page 5 battery id cycle counter byte 1 cycle counter byte 2 manufacturer id byte 1 registers e 2 to 1wire master device 1wire interface lockable t 1 through t b histogram bins time sample rate user byte user byte user byte user byte user byte user byte user byte user byte reserved address space page 2 sp2 or nv2 0 1 2 3 4 5 6 7 8 31 byte address 20h 21h 22h 23h 24h 25h 26h 27h 28h 3fh DS2435 021798 4/21 DS2435 addressable ram memory map figure 3 user byte reserved address space page 1 sp1 or nv1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 31 byte address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 1fh user byte user byte user byte user byte user byte user byte user byte user byte user byte user byte user byte user byte user byte user byte user byte user byte user byte user byte user byte user byte user byte user byte user byte status byte 1 status byte 2 reserved page 4 0 1 2 3 31 byte address 60h 61h 62h 63h 7fh registers t ( 1 / 2 c resolution) t (1 c resolution) cycle ctr byte 1 cycle ctr byte 2 page 5 0 31 byte address 80h 9fh battery id registers mfg id byte 1 mfg id byte 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 64h 65h 66h 67h 68h 69h 6ah 6bh 6ch 6dh 6eh 6fh 70h 71h 72h 73h 74h 75h 76h address space t 1 byte 1 t 1 byte 2 t 2 byte 1 t 2 byte 2 t 3 byte 1 t 3 byte 2 t 4 byte 1 t 4 byte 2 t 5 byte 1 t 5 byte 2 t 6 byte 1 t 6 byte 2 t 7 byte 1 t 7 byte 2 t 8 byte 1 t 8 byte 2 time byte 1 time byte 2 time byte 3 1 2 3 4 5 6 7 8 9 10 11 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh ta tb tc td te tf tg sample rate reserved address space DS2435 021798 5/21 DS2435 addressable ram memory map (cont'd) figure 3 user byte user byte page 3 sp3 or sram 0 1 31 byte address 40h 41h 5fh user byte ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DS2435 021798 6/21 overview time/temperature histogram periods of storage are normal for most battery applica- tions. during this storage time, little or no current is actu- ally drawn from the battery; however, batteries will lose capacity during this storage time due to parasitic side reactions in the cell, as well as other electrochemical mechanisms. this loss of capacity is termed selfdis- charge. since selfdischarge is the result of electrochemical reactions, its rate is dependent upon the cell tempera- ture. knowing the time spent in certain temperature ranges during the storage time of the battery, these tem- perature effects may be factored into a calculation of selfdischarge for the battery, thereby allowing a more accurate determination of retained battery capacity. the DS2435 measures, tabulates and stores this information in the battery pack. the DS2435 periodi- cally measures the battery temperature, and updates the appropriate temperature abino of the time/tempera- ture histogram with the time spent in that temperature range. the resulting histogram data would appear graphically as shown in figure 4. the DS2435 allows for eight temperature ranges, or bins, to be specified by fixing the values of the bin limits, ta through tg. once specified, the time spent in each of the bins (bin 1 being anything less than ta, bin 2 being temperature greater than or equal to ta but less than tb, etc., and bin 8 being anything greater than or equal to tg) is recorded (t 1 being the time spent in bin 1, t 2 the time spent in bin 2, etc.). using this information and data from the battery manufacturer regarding retained capacity, the actual battery capacity remaining may be closely approximated by the user. time/temperature histogram figure 4 bin number 1 2 3 4 5 6 7 8 bin limit temperatures ta tb tc td te tf tg t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t DS2435 021798 7/21 memory the DS2435's memory is divided into five pages, each page filling 32 bytes of address space. not all of the available addresses are used, however. refer to the memory map of figure 3 to see actual addresses which are available for use. the first three pages of memory consist of a scratchpad ram and then either a nonvolatile ram (pages 1 and 2) or sram (page 3). the scratchpads help insure data integrity when communicating over the 1wire bus. data is first written to the scratchpad where it can be read back. after the data has been verified, a copy scratchpad command will transfer the data to the ram (nv or sram). this process insures data integrity when modifying the memory. the fourth page of memory consists of registers which contain the measured temperature value, time/temper- ature histogram registers, elapsed time counter, and status registers for the device; these registers are made from sram cells. the fifth page of memory holds the id number for the device, the cycle count registers and the histogram bin limits in e 2 ram, making these registers nonvolatile under all power conditions. page 1 the first page of memory has 24 bytes. it consists of a scratchpad ram and a nonvolatile (e 2 ) ram. these 24 bytes may be used to store any data the user wishes; such as battery chemistry descriptors, manufacturing lot codes, gas gauge information, etc. the nonvolatile portion of this page may be locked to prevent data stored here from being changed inadver- tently. both the nonvolatile and the scratchpad portions are organized identically, as shown in the memory map of figure 3. in this page, these two portions are referred to as nv1 and sp1, respectively. page 2 the second page of memory has 8 bytes. it consists of a scratchpad ram and a nonvolatile (e 2 ) ram. these eight bytes may be used to store any data the user wishes, such as battery chemistry descriptors, manufacturing lot codes, gas gauge information, etc. page 3 the third page of memory has a full 32 bytes. it consists of a scratchpad ram and an sram. this address space may be used to store any data the user wishes, provided that, should the battery go dead and power to the DS2435 is lost, this data may also be lost without serious repercussions. data which must remain even if power to the DS2435 is lost should be placed in either page 1 or page 2. this section of memory may be used to store gas gauge and self discharge information. if the battery dies, and this information is lost, it is moot because the user can easily determine that the battery is dead. page 4 the fourth page of memory is used by the DS2435 to store the converted value of battery temperature, the time/temperature histogram data, and the elapsed time counter. a twobyte status register is also provided. temperature registers (60h61h) the DS2435 can measure temperature without external components. the resulting temperature measurement is placed into two temperature registers. these regis- ters are sram, and therefore will hold the values placed in them until the battery voltage falls below the minimum v dd specified. the first register, at address 60h, pro- vides 1 / 2 c resolution for temperatures between 0 c and 127 1 / 2 c, formatted as follows: 64 c32 c16 c8 c4 c2 c1 c 1 / 2 c the second register, at address 61h, provides 1 c reso- lution over the 40 c to +85 c range, formatted as fol- lows in the binary two's complement coding as shown in table 1: 7bit binary temp reading, shows 1 c increments sign bit 0 for positive, 1 for negative DS2435 021798 8/21 temperature/data relationships table 1 temperature digital output (binary) digital output (hex) +85 c 01010101 55h +25 c 00011001 19h 1 c 00000001 01h 0 c 00000000 00h 1 c 11111111 ffh 25 c 11100111 e7h 40 c 11011000 d8h status/control register (62h63h) the status register is a two byte register at addresses 62h and 63h (consisting of sram). address 62h is the least significant byte of the status register, and is cur- rently the only address with defined status bits; the other byte at address 63h is reserved for future use. the sta- tus register is formatted as follows: x x x x x lock nvb tb 62h lsb status register x x x x x x x x 63h where x = don't care tb = temperature busy flag. a1o = temperature conversion in progress; a0o = temperature conversion complete, valid data in tempera- ture register. nvb = nonvolatile memory busy flag. a1o = copy from scratchpad to nvram in progress, a0o = nonvolatile memory is not busy. a copy to nvram may take from 2 ms to 10 ms (tak- ing longer at lower supply voltages). lock = a1o indicates that nv1 is locked; a0o indicates that nv1 is unlocked. t 1 t 8 registers (64h73h) these registers hold the accumulated time values for the time/temperature histogram. t 1 corresponds to the time spent in histogram bin 1, t 2 the time spent in bin 2, etc., where the bins are defined by the limits set in ta tg as shown in figure 4. the format for the time value stored in these twobyte registers depends upon the sample rate, and is defined in the paragraph describing the sample rate parameter. t register (74n76h) this threebyte register is the elapsed time counter, for- matted as follows: 76h elapsed time counter 75h 2 23 min 2 22 min 2 21 min 2 20 min 2 19 min 2 18 min 2 17 min 2 16 min 32768 min 16384 min 8192 min 4096 min 2048 min 1024 min 512 min 256 min 74h 128 min 64 min 32 min 16 min 8 min 4 min 2 min 1 min the elapsed time counter has an lsb value of 1 minute; the total time which the counter can accommodate is 2 24 minutes, or 31.92 years. issuing any protocol to the DS2435 prevents the incre- menting of the elapsed time counter and histogram reg- isters, until the protocol is cleared by issuing a reset. therefore, it is imperative that any protocol issued to the DS2435 be followed by a reset (either after the protocol, if it requires no data, or immediately following data, if required by the protocol). this is necessary to avoid contention between the counter and histogram writing process and external processes. page 5 the fifth page of memory holds the battery manufac- turer id number, a twobyte counter for counting the number of battery charge/discharge cycles, histogram bin limits, and sample rate. id register (80h and 81h) the id register is a 16bit rom register that can con- tain a unique identification code, if purchased from dal- las semiconductor. this id number is programmed by dallas semiconductor, is unchangeable, and is unique to each customer. this id number may be used to assure that batteries containing a DS2435 have the same manufacturer id number as a charger configured to operate with that battery pack. this feature may be used to prevent charging of batteries for which the charging circuit has not been designed. sample rate data structure numbers express hours 1/8 1/4 1/2 1 ? ? ? ? lsb 4096 2048 1024 512 256 128 64 32 16 8 4 2 1 1/2 1/4 1/8 8192 4096 2048 1024 512 256 128 64 32 16 8 4 2 1/2 1/4 1 16384 4096 2048 1024 512 256 128 64 16 8 4 2 1/2 1 8192 32 16384 4096 2048 1024 512 256 128 64 16 8 4 2 1 8192 32 32768 ? 16384 4096 2048 1024 512 256 128 64 16 8 4 2 1/2 1 8192 32 sample rate data structure numbers express minutes lsb byte 2 byte 1 DS2435 021798 9/21 cycle counter (82h and 83h) the cycle counter register gives an indication of the number of charge/discharge cycles the battery pack has been through. this nonvolatile (e 2 ) register is incremented by the user through the use of a protocol to the DS2435, and is reset by another protocol. the counter is a straight binary counter, formatted as fol- lows: cycle counter msb lsb 65h 64h 32768 16384 8192 4096 1024 512 256 2048 128 64 32 16 8 4 2 0 tatg registers (84h8ah) these registers define the boundaries for the tempera- ture bins in the time/temperature histogram, as shown in figure 4. these temperature values are expressed in the same temperature format as shown in table 1. these limits therefore may be positive or negative val- ues, expressed with 1 c resolution. the bin limits must be specified in increasing order (i.e., ta DS2435 021798 10/21 example codes for 771 hours, 22.5 minutes with different sample rates table 2 sample rate t x byte 1 t x byte 2 1/8 00011000 00011011 1/4 00001100 00001101 1/2 00000110 00000110 1 00000011 00000011 memory function commands the protocols necessary for accessing the DS2435 are described in this section. these are summarized in table 3, and examples of memory functions are pro- vided in tables 4 and 5. page 1 through page 3 commands read scratchpad [11h] this command reads the contents of the scratchpad ram on the DS2435. this command is followed by a start byte address. after issuing this command and pro- viding the start address, the user may begin reading the data. the user may read data through the end of the scratchpad space (address 5fh), with any reserved data bits reading all logic 1's and after which the data read will be a repeat of address 5fh. write scratchpad [17h] this command writes to the scratchpad ram on the DS2435. this command is followed by a start byte address. after issuing this command and providing the start address, the user may begin writing data to the DS2435 scratchpad at the starting byte address. copy sp1 to nv1 [22h] this command copies the entire contents (24 bytes) of scratchpad 1 (sp1) to its corresponding nonvolatile memory (nv1). the nonvolatile ram memory of the DS2435 cannot be written to directly by the bus master; however, the scratchpad ram may be copied to the nonvolatile ram. this prevents accidental overwriting of the nonvolatile ram, and allows the data to be written first to the scratchpad, where it can be read back and verified before copying to the nonvolatile ram. this command does not use a start address; the entire con- tents of the scratchpad will be copied to the nonvolatile ram. the nvb bit will be set when the copy is in prog- ress. nv1 is made with e 2 type memory cells that will accept at least 50000 changes. copy sp2 to nv2 [25h] this command copies the entire contents (8 bytes) of sp2 (user bytes) to its corresponding nonvolatile memory (nv2). this command does not use a start address; the entire contents of sp2 will be copied to nv2. the nvb bit will be set when the copy is in prog- ress. nv2 is made with e 2 type memory cells that will accept at least 50000 changes. copy sp3 to sram [28h] this command copies the entire contents (32 bytes) of sp3 to its corresponding sram. this command does not use a start address; the entire contents of sp3 will be copied to the sram. copy nv1 to sp1 [71h] this command copies the entire contents (24 bytes) of nv1 to its corresponding scratchpad ram (sp1). this command does not use a start address; the entire con- tents of nv1 will be copied to sp1. the nonvolatile ram memory of the DS2435 cannot be read directly by the bus master; however, the nonvolatile ram may be copied to the scratchpad ram. copy nv2 to sp2 [77h] this command copies the entire contents (8 bytes) of nv2 (user bytes) to its corresponding scratchpad ram (sp2). this command does not use a start address; the entire contents of nv2 will be copied to sp2. the non- volatile ram memory of the DS2435 cannot be read directly by the bus master; however, the nonvolatile ram may be copied to the scratchpad ram. DS2435 021798 11/21 copy sram to sp3 [7ah] this command copies the entire contents (32 bytes) of sram to its corresponding scratchpad ram (sp3). this command does not use a start address; the entire contents of sram will be copied to sp3.the sram memory of the DS2435 cannot be read directly by the bus master; however, the sram may be copied to the scratchpad ram. lock nv1 [43h] this command prevents copying sp1 to nv1. this is done as an added measure of data security, preventing data from being changed inadvertently. nv1 may be copied up into sp1 while the part is locked. this allows nv1 to be read at any time. however, nv1 cannot be written to through a copy sp1 to nv1 command without first unlocking the DS2435. unlock nv1 [44h] this command unlocks nv1, to allow copying sp1 into nv1. this is done as an added measure of data security, preventing data from being changed inadvertently. page 4 and 5 commands convert t [d2h] this command instructs the DS2435 to initiate a tem- perature conversion cycle. this sets the tb flag. when the temperature conversion is done, the tb flag is reset and the current temperature value is placed in the tem- perature register. while a temperature conversion is taking place, all other memory functions are still avail- able for use. reset histogram [e1h] this command resets the accumulated time in all of the histogram temperature registers to zero. in addition, this command also resets the elapsed time counter to zero. this command does not use a start address; no further data is required. set clock [e6h] this command sets the elapsed time counter to a preset value. this command is followed by three bytes of data, which will be stored at addresses 74h76h. the trans- fer of this 3byte value will occur after reception of the 24th bit following the protocol, at which time the elapsed time counter will begin incrementing the counter regis- ters in 1 minute increments. write registers [efh] this command allows writing directly to the tatg reg- isters and the sample rate register. this command is fol- lowed by a start byte address. after issuing this com- mand and providing the start address, the user may begin writing the data. read registers [b2h] this command reads the contents of the registers in page 4 and 5. this command is followed by a start byte address. after issuing this command and providing the start address, the user may begin reading the data. the user may read data through the end of the register space (through address 76h in page 4, address 8bh in page 5), after which the data read will be all logic 1's. increment cycle [b5h] this command increments the value in the cycle counter register. this command does not use a start address; no further data is required. reset cycle counter [b8h] this command is used to reset the cycle counter regis- ter to zero, if desired. DS2435 021798 12/21 DS2435 command set table 3 instruction description protocol 1wire bus master status after issuing protocol 1wire bus data after issuing protocol page 1 through page 3 memory commands read scratchpad reads bytes from DS2435 scratchpad. 11h DS2435 021798 13/21 memory function example table 4 example: bus master writes 24 bytes of data to DS2435 scratchpad, then copies to it to nv1. master mode data (lsb first) comments tx reset reset pulse (480960 m s) rx presence presence pulse tx 17h issue awrite scratchpado command tx 00h start address tx <24 bytes> write 24 bytes of data to scratchpad tx reset reset pulse rx presence presence pulse tx 11h issue aread scratchpado command tx 00h start address rx <24 data bytes> read scratchpad data and verify tx reset reset pulse rx presence presence pulse tx 22h issue acopy sp1 to nv1o command rx DS2435 021798 14/21 1wire bus system the DS2435 1wire bus is a system which has a single bus master and one slave. the DS2435 behaves as a slave. the DS2435 is not able to be multidropped, unlike other 1wire devices from dallas semiconductor. the discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1wire signaling (signal types and tim- ing). hardware configuration the 1wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. to facilitate this, each device attached to the 1wire bus must have open drain or 3state outputs. the 1wire port of the DS2435 is open drain with an internal circuit equivalent to that shown in figure 6. the 1wire bus requires a pullup resistor of approximately 5k w . the idle state for the 1wire bus is high. if for any reason a transaction needs to be suspended, the bus must be left in the idle state if the transaction is to resume. if this does not occur and the bus is left low for more than 480 m s, all components on the bus will be reset. transaction sequence the protocol for accessing the DS2435 via the 1wire port is as follows: ? initialization ? memory function command ? transaction/data initialization all transactions on the 1wire bus begin with an initial- ization sequence. the initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). the presence pulse lets the bus master know that the DS2435 is on the bus and is ready to operate. for more details, see the ai/o signalingo section. hardware configuration figure 6 +5v r x t x 100 ohm mosfet 4.7k r x t x 5 m a typ. bus master DS2435 1wire port i/o signaling the DS2435 requires strict protocols to insure data integrity. the protocol consists of several types of signaling on one line: reset pulse, presence pulse, write 0, write 1, read 0, and read 1. all of these signals, with the exception of the presence pulse, are initiated by the bus master. the initialization sequence required to begin any com- munication with the DS2435 is shown in figure 7. a reset pulse followed by a presence pulse indicates the DS2435 is ready to send or receive data given the cor- rect memory function command. the bus master transmits (tx) a reset pulse (a low sig- nal for a minimum of 480 m s). the bus master then releases the line and goes into a receive mode (rx). the 1wire bus is pulled to a high state via the 5k pullup resistor. after detecting the rising edge on the i/o pin, the DS2435 waits 1560 m s and then transmits the presence pulse (a low signal for 60240 m s). DS2435 021798 15/21 read/write time slots DS2435 data is read and written through the use of time slots to manipulate bits and a command word to specify the transaction. write time slots a write time slot is initiated when the host pulls the data line from a high logic level to a low logic level. there are two types of write time slots: write one time slots and write zero time slots. all write time slots must be a mini- mum of 60 m s in duration with a minimum of a 1 m s recov- ery time between individual write cycles. the DS2435 samples the i/o line in a window of 15 m s to 60 m s after the i/o line falls. if the line is high, a write one occurs. if the line is low, a write zero occurs (see figure 6). for the host to generate a write one time slot, the data line must be pulled to a logic low level and then released, allowing the data line to pull up to a high level within 15 m s after the start of the write time slot. for the host to generate a write zero time slot, the data line must be pulled to a logic low level and remain low for the duration of the write time slot. read time slots the host generates read time slots when data is to be read from the DS2435. a read time slot is initiated when the host pulls the data line from a logic high level to logic low level. the data line must remain at a low logic level for a minimum of 1 m s; output data from the DS2435 is then valid for the next 14 m s maximum. the host there- fore must stop driving the i/o pin low in order to read its state 15 m s from the start of the read slot (see figure 8). by the end of the read time slot, the i/o pin will pull back high via the external pullup resistor. all read time slots must be a minimum of 60 m s in duration with a minimum of a 1 m s recovery time between individual read slots. figure 9 shows that the sum of t init , t rc , and t sample must be less than 15 m s. figure 10 shows that system timing margin is maximized by keeping t init and t rc as small as possible and by locating the master sample time towards the end of the 15 m s period. initialization procedure areset and presence pulseso figure 7 master t x areset pulseo 480 m s minimum 980 m s maximum master r x 480 m s minimum v cc gnd DS2435 waits 15 - 60 m s DS2435 t x apresence pulseo 60 - 240 m s line type legend: bus master active low both bus master and DS2435 active low DS2435 active low resistor pull-up 1-wire bus DS2435 021798 16/21 read/write timing diagram figure 8 1wire bus master write a0o slot master write a1o slot 60 m s DS2435 021798 18/21 absolute maximum ratings* voltage on any pin relative to ground 0.3v to +7.0v operating temperature 40 c to +85 c storage temperature 55 c to +125 c soldering temperature 260 c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (40 c to +85 c) parameter symbol condition min typ max units notes supply voltage v dd i/o functions nv copy functions 1 / 2 c accurate temp. conversions 2.5 2.7 3.6 6.4 6.4 6.4 v 1 data pin v i/o 0.3 v dd +0.3 v dc electrical characteristics (40 c to +85 c; v dd =3.6v to 6.4v) parameter symbol condition min typ max units notes temperature accuracy (=t actual t measured ) t a =0 c to 70 c t a =40 c to 0 c and +70 c to +85 c 1 / 2 see typical curve c 3 input logic high v ih v dd =4.8v 2.2 v dd +0.3 v input logic low v il v dd =4.8v 0.3 +0.8 v sink current i l v i/o =0.4v 4.0 ma standby current i q clock running 10 25 m a 4 active current i dd temp conversions 1.5 ma 4 input resistance r i 500 k w 2 notes: 1. temperature conversion will work with 2 c accuracy down to v dd =2.7v. 2. i/o line in ahizo state and i i/o =0. resistance specified from i/o to ground. 3. see typical curve for specification limits outside 0 c to 70 c range. thermometer error reflects sensor accuracy as tested during calibration. 4. specified with dq=v dd . 5. the bus should not remain idle for more than 20 ms between bits or between a bit and a reset. DS2435 021798 19/21 ac electrical characteristics: 1wire interface (40 c to +85 c; v dd =3.6v to 6.4v) parameter symbol min typ max units notes temperature conversion time t conv 250 500 ms time slot t slot 60 120 m s recovery time t rec 1 20000 m s 5 write 0 low time t low0 60 120 m s write 1 low time t low1 1 15 m s read data valid t rdv 15 m s reset time high t rsth 480 m s reset time low t rstl 480 m s presence detect high t pdhigh 15 60 m s presence detect low t pdlow 60 240 m s capacitance c in/out 25 pf timer accuracy 10 % 1wire write one time slot start of next cycle t rec t low1 t slot 1wire write zero time slot start of next cycle t rec t slot t low0 DS2435 021798 20/21 1-wire read zero time slot start of next cycle t rec t slot t rdv 1-wire reset pulse reset pulse from host presence detect 1-wire presence detect t rstl t rsth t pdhigh t pdlow DS2435 021798 21/21 typical performance curve 55 35 15 5 25 45 65 85 105 125 5 4 3 2 1 1 2 3 upper limit specification typical lower limit specification DS2435 digital thermometer and thermostat temperature reading error error (deg. c) temperature (deg. c) error |
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